1. Field of the Invention
The present invention relates to a method for reducing via shorts on integrated circuits, and, more particularly, reducing via shorts while permitting verification of the final design by standard verification tools.
2. Description of the Related Art
Conventional integrated circuit manufacturing technologies suffer from reduced yields due to via shorts, i.e., electrical shorts. A via is a small hole used to connect electrical conducting nets from one layer of an integrated circuit to another layer. Some via shorts are caused by a phenomenon called via flaring. Via flaring occurs in areas where large number of vias are clustered together.
An integrated circuit with a via short is unusable. Integrated circuits containing a via short must be discarded. In some cases, when the number of discarded integrated circuits is large, the integrated circuit is redesigned to remove the vias causing the short. A redesign of an integrated circuit is time consuming and costly.
A conventional solution to a via short is to delete (or remove) shorting vias by applying a shape algorithm to the corresponding integrated circuit shapes database. However, for example, in a hierarchical shapes database where one cell contains all the via shapes of the database, a conventional shape algorithm may result in the deletion of all via shapes in the design.
Another conventional solution to a via short is to flatten the hierarchical design, that the flat design has a single cell with all the design shapes. A shape algorithm may then delete only those vias that might short. However, the flat design layout is impossible to compare to the design schematic, i.e., using standard layout versus schematic (hereinafter LVS ) verification methods, since the design schematic hierarchy is different from the design layout hierarchy.